In the fabrication of integrated circuits it is often necessary to form a large number of transistors on a single chip. These transistors are interconnected to form logic gates, flip-flops, memory cells and a wide variety of other devices. A gate array is an array of transistor circuits which utilize the same base cell for many different applications. In this configuration, only the final interconnection levels of the multilevel device are specifically designed for any given application. The initial levels, known as the base cell, are the same for each implementation.
One type of gate array includes moat regions which comprise p-doped silicon and other moat regions which comprise n-doped silicon. These regions can be used to create p-channel and n-channel devices, respectively. One example of an application which uses both conductivity type channels is a CMOS (complementary metal oxide semiconductor) device.
Many gate array applications require the gates of adjacent base cells to be connected electrically. This electrical connection is often made when the gates are formed during the base cell fabrication. Connected gates are common in CMOS devices, for example.
The portions of the cell, including the gate and the moat regions, are connected into the final transistor configurations by routing conductive lines over the cells of the array which covered by an insulating layer. Contacts are formed in the insulating layers and thereby the desired circuits are formed. Multiple layers of metal lines and insulating layers may be used.
The metal interconnect lines are placed in a grid-like fashion over the base cell. Each line is substantially parallel or perpendicular to and evenly spaced from adjacent lines on the grid pattern. To avoid two separate lines crossing, the interconnects must be routed around each other or another interconnect level must be formed. This creates an added cost in either area or in the n-tuber of levels.
Accordingly, improvements which overcome any or all of the problems are presently desirable.